16-mbit (1m x 16) static ram cy7c1061bv33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05693 rev. *b revised august 3, 2006 features ?high speed ?t aa = 10 ns ? low active power ? 990 mw (max.) ? operating voltages of 3.3 0.3v ? 2.0v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? available in pb-free and non pb-free 54-pin tsop ii package functional description the cy7c1061bv33 is a high-performance cmos static ram organized as 1,048,576 words by 16 bits. writing to the device is accomplished by enabling the chip (ce low) while forcing the write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). reading from the device is accomplished by enabling the chip by taking ce low while forcing the output enable (oe ) low and the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the ba ck of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low and we low). the cy7c1061bv33 is available in a 54-pin tsop ii package with center power and ground (revolutionary) pinout. logic block diagram 15 16 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 1m x 16 array a 0 a 12 a 14 a 13 a a a 17 a 18 a 10 a 11 i/o 0 ?i/o 7 oe i/o 8 ?i/o 15 ce we ble bhe a 9 a 19 we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 43 42 16 15 29 30 a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe a 3 a 4 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 i/o 6 i/o 4 i/o 5 i/o 7 a 16 a 15 ble v cc i/o 14 i/o 13 i/o 12 i/o 10 i/o 9 i/o 8 a 14 a 13 a 12 a 11 a 9 a 10 44 46 45 47 50 49 48 51 53 52 54 v ss v cc a 19 a 18 v cc v cc v ss v ss nc v cc i/o 11 v ss dnu/v cc dnu/v ss 54-pin tsop ii (top view) notes: 1. dnu/v cc pin (#16) has to be left floating or connected to v cc and dnu/v ss pin (#40) has to be left floating or connected to v ss to ensure proper application. 2. nc ? no connect pins are not connected to the die pin configurations [1, 2] [+] feedback [+] feedback
cy7c1061bv33 document #: 38-05693 rev. *b page 2 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v cc to relative gnd [3] ?0.5v to +4.6vdc voltage applied to outputs in high-z state [3] ....................................?0.5v to v cc + 0.5v dc input voltage [3] ................................ ?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma selection guide ?10 ?12 unit maximum access time 10 12 ns maximum operating current commercial 275 260 ma industrial 275 260 maximum cmos standby current commercial/industrial 50 50 ma operating range range ambient temperature v cc commercial 0c to +70c 3.3v 0.3v industrial ?40c to +85c dc electrical characteristics over the operating range parameter description test conditions ?10 ?12 unit min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [3] ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc commercial 275 260 ma industrial 275 260 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 70 70 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 commercial/ industrial 50 50 ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 6 pf c out i/o capacitance 8 pf thermal resistance [4] parameter description test conditions 54-pin tsop-ii unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 49.95 c/w jc thermal resistance (j unction to case) 3.34 c/w notes: 3. v il (min.) = ?2.0v and v ih (max) = v cc + 0.5v for pulse durations of less than 20 ns. 4. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
cy7c1061bv33 document #: 38-05693 rev. *b page 3 of 9 ac test loads and waveforms [5] ac switching characteristics over the operating range [6] parameter description ?10 ?12 unit min. max. min. max. read cycle t power v cc (typical) to the first access [7] 11ms t rc read cycle time 10 12 ns t aa address to data valid 10 12 ns t oha data hold from address change 3 3 ns t ace ce low to data valid 10 12 ns t doe oe low to data valid 5 6 ns t lzoe oe low to low-z 1 1 ns t hzoe oe high to high-z [8] 56ns t lzce ce low to low-z [8] 33ns t hzce ce high to high-z [8] 56ns t pu ce low to power-up [9] 00ns t pd ce high to power-down [9] 10 12 ns t dbe byte enable to data valid 5 6 ns t lzbe byte enable to low-z 1 1 ns t hzbe byte disable to high-z 5 6 ns notes: 5. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0v). as soon as 1ms (t power ) after reaching the minimum operating v dd , normal sram operation can begin including reduction in v dd to the data retention (v ccdr , 2.0v) voltage. 6. test conditions assume signal transition time of 3 ns or less , timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and specified transmission line loads. test conditio ns for the read cycle use output loading shown in part a) of the ac test l oads, unless specified otherwise. 7. this part has a voltage regulator which steps down the voltage from 3v to 2v internally. t power time has to be provided initially before a read/write operation is started. 8. t hzoe , t hzce , t hzwe , t hzbe and t lzoe , t lzce , t \lzwe , t lzbe are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 9. these parameters are guaranteed by design and are not tested. 10. the internal write time of the me mory is defined by the overlap of ce low and we low. chip enables must be active and we and byte enables must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing sho uld be referenced to the leading edge of the signal that terminates the write. 11. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 90% 10% 3.3v gnd 90% 10% all input pulses 3.3v output 5 pf* including jig and scope (a) (b) r1 317 ? r2 351 ? rise time > 1v/ns fall time: > 1v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5v 30 pf* * capacitive load consists of all com- ponents of the test environment. [+] feedback [+] feedback
cy7c1061bv33 document #: 38-05693 rev. *b page 4 of 9 write cycle [10, 11] t wc write cycle time 10 12 ns t sce ce low to write end 7 8 ns t aw address set-up to write end 7 7 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 7 8 ns t sd data set-up to write end 5.5 6 ns t hd data hold from write end 0 0 ns t lzwe we high to low-z [8] 33ns t hzwe we low to high-z [8] 56ns t bw byte enable to end of write 7 8 ns t ha address hold from write end 0 0 ns ac switching characteristics over the operating range [6] (continued) parameter description ?10 ?12 unit min. max. min. max. data retention waveform 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc switching waveforms read cycle no. 1 [12, 13] notes: 12. device is continuously selected. oe , ce , bhe and/or bhe = v il . 13. we is high for read cycle. previous data valid data valid t rc t aa t oha address data out [+] feedback [+] feedback
cy7c1061bv33 document #: 38-05693 rev. *b page 5 of 9 read cycle no. 2 (oe controlled) [13, 14] write cycle no. 1 (ce controlled) [15, 16] notes: 14. address valid prior to or coincident with ce transition low. 15. data i/o is high-impedance if oe or bhe and/or ble = v ih . 16. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o address ce we bhe, ble t [+] feedback [+] feedback
cy7c1061bv33 document #: 38-05693 rev. *b page 6 of 9 write cycle no. 2 (ble or bhe controlled) write cycle no. 3 (we controlled, oe low) [15, 16] switching waveforms (continued) t hd t sd t bw t sa t ha t aw t pwe t wc t sce datai/o address bhe ,ble we ce t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe [+] feedback [+] feedback
cy7c1061bv33 document #: 38-05693 rev. *b page 7 of 9 truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high-z high-z power-down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high-z read lower bits only active (i cc ) l l h h l high-z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high-z write lower bits only active (i cc ) l x l h l high-z data in write upper bits only active (i cc ) l h h x x high-z high-z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 10 cy7c1061bv33-10zc 51-85160 54-pin tsop ii commercial cy7c1061bv33-10zi industrial cy7c1061bv33-10zxc 54-pin tsop ii (pb-free) commercial cy7c1061bv33-10zxi industrial 12 CY7C1061BV33-12ZC 54-pin tsop ii commercial cy7c1061bv33-12zi industrial cy7c1061bv33-12zxc 54-pin tsop ii (pb-free) commercial cy7c1061bv33-12zxi industrial [+] feedback [+] feedback
cy7c1061bv33 document #: 38-05693 rev. *b page 8 of 9 all products and company names mentioned in this document may be the trademarks of their respective holders. package diagram 51-85160-** 54-pin tsop ii (51-85160) [+] feedback [+] feedback
cy7c1061bv33 document #: 38-05693 rev. *b page 9 of 9 document history page document title: cy7c1061bv33 16-mbit (1m x 16) static ram document number: 38-05693 rev. ecn no. issue date orig. of change description of change ** 283950 see ecn rkf new data sheet *a 309453 see ecn rkf final data sheet *b 492137 see ecn nxr removed 8 ns speed bin changed the description of i ix from input load current to input leakage current in dc electrical characteristics table updated the ordering information table [+] feedback [+] feedback
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